Between schematic confidence and layout reality

Find the few parasitics that matter.

PCP ranks capacitive and resistive layout parasitics by their impact on your analog or mixed-signal circuit — using the netlists and simulations you already have.

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Swiss company · Patent pending · 5 international (PCT) applications

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The problem

Countless parasitics. A handful matter. Finding them is still manual.

01

Too many to reason about.

Extraction adds thousands to millions of capacitors and resistors. Simulation shows the symptom, not the cause.

02

Found by trial and error.

Post-layout results tell you performance dropped — not which parasitics did it. Engineers hunt through iterations, close to tape-out.

03

Expertise is leaving.

Knowing which parasitics are dangerous has lived in senior engineers' heads. ~30% of Europe's semiconductor workforce retires by 2030.1

32% → 5% Chips working at first silicon, all causes: 32% in 2020 → 5% in 2026.2

Confirmed by the people who live it: in our 2024 survey, 9 of 9 analog/mixed-signal verification engineers at leading chipmakers said they meet this problem often or sometimes — none said rarely.3

  1. ¹ European Chips Skills Academy, Skills Strategy 2025.
  2. ² Wilson Research Group functional verification study 2026 (n = 604), all causes.
  3. ³ Rotosi survey, Nov 2024 (n = 9).

PCP · Parasitic Component Pruning

Ranked by impact on your circuit — not by size.

Step 1

Your files

Netlists, extracted parasitics, simulation results.

Step 2

Risk ranking

The few that matter, ranked by impact.

Step 3

Fix what moves your specs

Spend the next layout iteration on the parasitics that actually shift performance — not on guesswork.

Security

Your design stays with you.

PCP runs on your own machines, with no network connection. No upload, no cloud. PCP itself needs no PDK — it works on your existing extraction and simulation results. It does not modify your design and works with Cadence® Spectre® and ngspice.

  • On-premises
  • No network
  • No PDK needed
  • Read-only

Want to see PCP on a real design flow? Request a technical demo →

Proof

open-source designs tested

Tested in the open.

PCP is verified on public chip designs from the open-source community — different processes, formats and extraction tools. Test designs with a known failure came back within spec after applying PCP's advice.

See one example

Open-source amplifier, SkyWater SKY130: settling time 113 ns → 73 ns (limit 76 ns) after acting on PCP's ranking.

Rotosi's own tests. Details on request.

Work with us

Talk to us.

Design teams

Available as a team licence for analog and mixed-signal design teams. Start with a scoped evaluation on one of your blocks.

Ask about an evaluation

Partners

Design-service companies: use PCP on client projects. Institutes and foundries: joint validation on your designs.

Discuss a partnership

Investors

Our aim: make parasitic review as routine as LVS and DRC. We'd be glad to share our deck.

Ask for the deck
ewa.augustyniak@rotosi.ch Küsnacht, Zurich, Switzerland
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